Leseprobe
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Design and Test Strategies for 2D/3D Integration for NoC-based Multicore Architectures
Jimson Mathew, Kanchan Manna
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Springer International Publishing 
Naturwissenschaften, Medizin, Informatik, Technik / Elektronik, Elektrotechnik, Nachrichtentechnik
Beschreibung
This book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems. It gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of the Integer Line Programming (ILP) technique for smaller benchmarks and a Particle Swarm Optimization (PSO) to get a near optimal mapping and test schedule for bigger benchmarks. The PSO-based approach is also augmented with several innovative techniques to get the best possible solution. The tradeoff between performance (communication or test time) of the system and thermal-safety is also discussed, based on designer specifications.
- Provides a single-source reference to design and test for circuit and system-level approaches to (NoC) based multicore systems;
- Gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling in (NoC) based multicore systems;
- Organizes chapters systematically and hierarchically, rather than in an ad hoc manner, covering aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.
Kundenbewertungen
TSV placement for 3D-NoC-based multicore systems, Network-on-Chip Designs and Tests, Temperature-aware design and test for 2D and 3D NoCs, Designing 2D and 3D Network-on-Chip Architectures, Scalable Multi-core Architecture Design